1. Field of the Invention
The present invention relates to a ferroelectric memory device, and more specifically, to a ferroelectric memory device including an extended memory unit to store additional information such as device information.
2. Description of the Prior Art
Generally, a ferroelectric random access memory (hereinafter, referred to as ‘FRAM’) has attracted considerable attention as next generation memory device because it has a data processing speed as fast as a DRAM (Dynamic Random Access Memory) and conserves data even after the power is turned off.
The FRAM includes capacitors similar to the DRAM, but the capacitors have a ferroelectric substance for utilizing the characteristic of a high residual polarization of the ferroelectric substance in which data is not low even after eliminating an electric field applied thereto.
FIG. 1 is a characteristic curve illustrating a hysteresis loop of a general ferroelectric substance. As shown in FIG. 1, a polarization induced by an electric field does not vanish but keeps some strength (‘d’ or ‘a’ state) even after the electric field is cleared due to existence of a residual (or spontaneous) polarization. These ‘d’ and ‘a’ states may be assigned to binary values of ‘1’ and ‘0’ for use as a memory cell.
FIG. 2 is a structural diagram illustrating a unit cell of the FRAM device. As shown in FIG. 2, the unit cell of the conventional FRAM is provided with a bitline BL arranged in one direction and a wordline WL arranged in another direction vertical to the bitline BL. A plateline PL is arranged parallel to the wordline and spaced at a predetermined interval. The unit cell is also provided with a transistor T1 having a gate connected to an adjacent wordline WL and a source connected to an adjacent bitline BL, and a ferroelectric capacitor FC1 having the first terminal of the two terminals connected to the drain terminal of the transistor T1 and the second terminal of the two terminals connected to the plateline PL.
FIG. 3a is a timing diagram illustrating a write mode of the conventional FRAM.
Referring to FIG. 3a, when a chip enable signal CSBpad applied externally transits from a high to low level and simultaneously a write enable signal WEBpad also transits from a high to low level, the array is enabled to start a write mode. Thereafter, when an address is decoded in a write mode, a pulse applied to a corresponding wordline transits from a “low” to “high” level, thereby selecting the cell.
In order to write a binary logic value “1” in the selected cell, a “high” signal is applied to a bitline BL while a “low” signal is applied to a plateline PL. In order to write a binary logic value “0” in the cell, a “low” signal is applied to a bitline BL while a “high” signal is applied to a plateline PL.
FIG. 3b is a timing diagram illustrating a read mode of the conventional FRAM. Referring to FIG. 3b, when a chip enable signal CSBpad externally transits from a “high” to “low” level, all bitlines are equalized to a “low” level by an equalization signal before selection of a required wordline.
After each bitline is deactivated, an address is decoded to transit a signal on the required wordline from a “low” to “high” level, thereby selecting a corresponding unit cell. A “high” signal is applied to a plateline of the selected cell to cancel a data Qs corresponding to the logic value “1” stored in the FRAM. If the logic value “0” is stored in the FRAM, a corresponding data Qns will not be destroyed.
The destroyed and non-destroyed data output different values, respectively, according to the above-described hysteresis loop characteristics. As a result, a sense amplifier senses logic values “1” or “0”. In other words, as shown in the hysteresis loop of FIG. 1, the state moves from ‘d’ to ‘f’ when the data is destroyed while the state moves from ‘a’ to ‘f’ when the data is not destroyed.
As a result, the destroyed data amplified by the enabled sense amplifier outputs a logic value “1” while the non-destroyed data amplified by the sense amplifier outputs a logic value “0”. The original data is destroyed after the sense amplifier amplifies the data. Accordingly, when a “high” signal is applied to the required wordline, the plateline is disabled from “high” to “low”, thereby recovering the original data.
The conventional ferroelectric memory device does not comprise an extended memory unit in the memory device to store information such as device ID, manufacturer code and security code. As a result, an additional memory unit to store the additional information is required outside of the memory.
In the systems using a conventional ferroelectric memory device, there is installed an Error Correcting Circuit (ECC) to repair a fail cell of the memory device in an external system of the memory. Therefore, the system requires to perform an error-correcting operation on fail cells, thereby degrading the operation performance.